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DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
Each multivibrator of the LS221 features a negative-transition-triggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger input circuitry for B input allows jitter-free triggering for inputs as slow as 1 volt / second, providing the circuit with excellent noise immunity. A high immunity to VCC noise is also provided by internal latching circuitry. Once triggered, the outputs are independent of further transitions of the inputs and are a function of the timing components. The output pulses can be terminated by the overriding clear. Input pulse width may be of any duration relative to the output pulse width. Output pulse width may be varied from 35 nanoseconds to a maximum of 70 s by choosing appropriate timing components. With Rext = 2.0 k and Cext = 0, a typical output pulse of 30 nanoseconds is achieved. Output rise and fall times are independent of pulse length. Pulse width stability is achieved through internal compensation and is virtually independent of VCC and temperature. In most applications, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCC ranges for greater than six decades of timing capacitance (10 pF to 10 F), and greater than one decade of timing resistance (2.0 to 70 k for the SN54LS221, and 2.0 to 100 k for the SN74LS221). Pulse width is defined by the relationship: tw(out) = CextRext ln 2.0 0.7 Cext Rext; where tW is in ns if Cext is in pF and Rext is in k . If pulse cutoff is not critical, capacitance up to 1000 F and resistance as low as 1.4 k may be used. The range of jitter-free pulse widths is extended if VCC is 5.0 V and 25C temperature.
SN54/74LS221
DUAL MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS
LOW POWER SCHOTTKY
J SUFFIX CERAMIC CASE 620-09
16 1
16 1
N SUFFIX PLASTIC CASE 648-08
16 1
D SUFFIX SOIC CASE 751B-03
* SN54LS221 and SN74LS221 is a Dual Highly Stable One-Shot * Overriding Clear Terminates Output Pulse * Pin Out is Identical to SN54 / 74LS123
ORDERING INFORMATION
SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC
(TOP VIEW)
VCC 16 1 Rext/ 1 Cext Cext 15 14 Q Q CLR 1Q 13 2Q 12 2 CLR 11 2B 10 2A 9 VCC CLR Q Q 4 1Q 5 2Q 6 2 Cext 8 7 2 Rext/ GND Cext Cext Rext + R/C L X X H H
*
FUNCTION TABLE (EACH MONOSTABLE)
INPUTS CLEAR A X H X L L B X X L H H MAXIMUM OUTPUT PULSE LENGTH 49 s 70 s OUTPUTS Q L L L Q H H H
1 1A
2 1B
3 1 CLR
*See operational notes -- Pulse Trigger Modes
TYPE SN54LS221 SN74LS221
positive logic: Low input to clear resets Q low and positive logic: Q high regardless of dc levels at A positive logic: or B inputs.
TYPICAL POWER DISSIPATION 23 mW 23 mW
FAST AND LS TTL DATA 5-1
SN54/74LS221
OPERATIONAL NOTES Once in the pulse trigger mode, the output pulse width is determined by tW = RextCextIn2, as long as Rext and Cext are within their minimum and maximum valves and the duty cycle is less than 50%. This pulse width is essentially independent of VCC and temperature variations. Output pulse widths varies typically no more than 0.5% from device to device. If the duty cycle, defined as being 100 * tW where T is the T input period of the input pulse, rises above 50%, the output pulse width will become shorter. If the duty cycle varies between low and high valves, this causes the output pulse width to vary in length, or jitter. To reduce jitter to a minimum, Rext should be as large as possible. (Jitter is independent of Cext). With Rext = 100K, jitter is not appreciable until the duty cycle approaches 90%. Although the LS221 is pin-for-pin compatible with the LS123, it should be remembered that they are not functionally identical. The LS123 is retriggerable so that the output is dependent upon the input transitions once it is high. This is not the case for the LS221. Also note that it is recommended to externally ground the LS123 Cext pin. However, this cannot be done on the LS221. The SN54LS/74LS221 is a dual, monolithic, non-retriggerable, high-stability one shot. The output pulse width, tW can be varied over 9 decades of timing by proper selection of the external timing components, Rext and Cext. Pulse triggering occurs at a voltage level and is, therefore, independent of the input slew rate. Although all three inputs have this Schmitt-trigger effect, only the B input should be used for very long transition triggers (1.0 V/s). High immunity to VCC noise (typically 1.5 V) is achieved by internal latching circuitry. However, standard VCC bypassing is strongly recommended. The LS221 has four basic modes of operation. Clear Mode: If the clear input is held low, irregardless of the previous output state and other input states, the Q output is low.
Inhibit Mode: If either the A input is high or the B input is low, once the Q output goes low, it cannot be retriggered by other inputs. Pulse Trigger Mode: A transition of the A or B inputs as indicated in the functional truth table will trigger the Q output to go high for a duration determined by the tW equation described above; Q will go low for a corresponding length of time. The Clear input may also be used to trigger an output pulse, but special logic preconditioning on the A or B inputs must be done as follows: Following any output triggering action using the A or B inputs, the A input must be set high OR the B input must be set low to allow Clear to be used as a trigger. Inputs should then be set up per the truth table (without triggering the output) to allow Clear to be used a trigger for the output pulse. If the Clear pin is routinely being used to trigger the output pulse, the A or B inputs must be toggled as described above before and between each Clear trigger event. Once triggered, as long as the output remains high, all input transitions (except overriding Clear) are ignored. Overriding Clear Mode: If the Q output is high, it may be forced low by bringing the clear input low.
FAST AND LS TTL DATA 5-2
SN54/74LS221
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits Symbol S bl VT+ VT T- VT+ VT T- VIH VIL VIK VOH Parameter P Positive-Going Threshold Voltage at C Input Negative-Going Threshold g g Voltage at C Input Positive-Going Threshold Voltage at B Input Negative-Going Threshold g g Voltage at B Input Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Voltage 54 Output HIGH Voltage 74 54 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Input A Input B Clear Short Circuit Current (Note 1) Power Supply Current Quiescent Triggered - 20 4.7 19 - 0.4 - 0.8 - 0.8 - 100 11 27 0.35 0.5 20 IIH V A mA 2.7 3.4 0.25 0.4 V V 2.5 3.4 0.8 - 1.5 V V VCC = MIN IOH = MAX MIN, IOL = 4.0 mA IOL = 8.0 mA 54 74 0.7 0.8 2.0 0.7 V 54 74 0.7 0.7 Min Typ 1.0 0.8 0.8 1.0 0.9 0.9 2.0 Max 2.0 Unit Ui V V V V V V V VCC = MIN Guaranteed Input HIGH Voltage for A Input Guaranteed Input LOW Voltage for p g A Input VCC = MIN, IIN = - 18 mA VCC = MIN VCC = MIN VCC = MIN Test C di i T Conditions
VCC = MIN
VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V
IIL
mA
VCC = MAX, VIN = 0.4 V
IOS ICC
mA
VCC = MAX VCC = MAX
mA
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA 5-3
SN54/74LS221
AC CHARACTERISTICS (VCC = 5.0 V, TA = 25C)
Symbol S bl tPLH From (Input) A B A tPHL tPHL tPLH B Clear Clear To (Output) Q Q Q Q Q Q 70 20 tW(out) A or B Q or Q 600 6.0 670 6.9 750 7.5 ms Limits Min Typ 45 35 50 40 35 44 120 47 Max 70 ns 55 80 ns 65 55 65 150 70 ns ns ns pF, CL = 15 pF, See Figure 1 Cext = 80 pF, Rext = 2.0 Cext = 0, Rext = 2.0 k Cext = 100 pF, Rext = 10 k Cext = 1.0 F, Rext = 10 k Cext = 80 pF, Rext = 2.0 pF F 20 Unit Ui Test C di i T Conditions
AC SETUP REQUIREMENTS (VCC = 5.0 V, TA = 25C)
Limits Symbol S bl Parameter P Rate of Rise or Fall of Input Pulse dv/dt d /d Schmitt, B Logic Input, A Input Pulse Width tW ts Rext Cext Clear-Inactive-State Setup Time 54 External Timing Resistance 74 External Timing Capacitance Output Duty Cycle RT = 2.0 k RT = MAX Rext 50 90 % 1.4 0 100 1000 F A or B, tW(in) Clear, tW (clear) 40 40 15 1.4 70 k ns ns 1.0 1.0 V/s V/s Min Typ Max Unit Ui
FAST AND LS TTL DATA 5-4
SN54/74LS221
AC WAVEFORMS
tW(in) B INPUT 60 ns CLEAR tPLH Q OUTPUT tPHL Q OUTPUT A INPUT IS LOW.
TRIGGER FROM B, THEN CLEAR -- CONDITION 1
3V 1.3 V 0V 3V tPHL 0V VOH VOL VOH VOL
tPLH
3V B INPUT 60 ns CLEAR Q OUTPUT A INPUT IS LOW.
TRIGGER FROM B, THEN CLEAR -- CONDITION 2
0V 1.3 V 3V 0V VOH VOL
B INPUT 50 ns CLEAR TRIGGERED Q OUTPUT NOT TRIGGERED A INPUT IS LOW. tW(out) 0 ts
3V 0V 3V 0V VOH VOL
CLEAR OVERRIDING B, THEN TRIGGER FROM B
B INPUT 50 ns CLEAR 50 ns 1.3 V
3V 0V 3V 0V
Q OUTPUT A INPUT IS LOW.
TRIGGERING FROM POSITIVE TRANSITION OF CLEAR
VOH VOL
Figure 1
FAST AND LS TTL DATA 5-5

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